1. Field of the Invention
The present invention is generally related to non-volatile semiconductor memory devices and to methods of programming non-volatile semiconductor memory device.
A claim of priority is made to Korean Patent Application No. 10-2005-54753, filed Jun. 24, 2005, the subject matter of which is incorporated by reference in its entirety.
2. Description of the Related Art
Generally, in a non-volatile semiconductor memory device (e.g., a NAND flash memory device), data is programmed by altering the threshold voltage of a selected memory cell by applying so-called “pass” and “program” voltages to word lines connected to gates of non-volatile memory cells.
FIG. 1 is a diagram showing a conventional non-volatile semiconductor memory device, and FIG. 2 is a voltage-timing diagram showing a sequence of program loops LOOP <0-2> executed by the device of FIG. 1. Each of the of the program loops LOOP <0-2> includes a programming operation T01, T11 and T21, and verify read operation T02, T12 and T22.
As shown in FIG. 1, the conventional non-volatile semiconductor memory device includes a non-volatile memory cell array 10, row decoder 20, a pre-decoder 30, a high voltage generation unit 50, and a page buffer 60.
The non-volatile memory cell array 10 includes a memory cell string connected between a bit line BL and a common source line CSL. More specifically, the memory cell string includes a select transistor ST, a plurality of non-volatile memory cells MC<1-32>, and a ground transistor GT, all connected in series between the bit line BL and the common source line CSL.
The row decoder 20 includes a boosting circuit 21 and a plurality of transmission transistors TT. One of the transmission transistors TT is connected between a global string select line GSSL and a string select line SSL, and another of the transmission transistors TT is connected between a global ground select line GGSL and a string ground select line SGSL. The remaining transmission transistors TT are respectively connected between global word lines <1-32> and word lines SWL <1-32>. The boosting circuit 21 provides the block gating signal BKWL of FIG. 2 to the gates of the transmission transistors TT in accordance with pass and program voltages VPASS and VPGM, a block address BKADD and a boosting control signal CON11.
The high voltage generation unit 50 generates the pass voltage VPASS and the program voltage VPGM. In addition, although not shown in FIG. 1, the high voltage generation unit 50 generates a read voltage (VREAD, FIG. 2) which is used by the during reading of the non-volatile memory device.
The pre-decoder 30 provides voltages to select one of the global word lines GWL<1:32>, and to activate a global string select line GSSL, and a global ground select line GGSL. As shown in FIG. 2, a selected word line SWL (SELECTED) corresponding to a selected global word line GWL is applied with a program voltage VPGM <1> in response to the block selection signal BKWL, and the non-volatile memory cell connected to the selected word line SWL (SELECTED) is programmed accordingly. The remaining word lines SWL (NON-SELECTED) are applied with the pass voltage VPASS in response to the block selection signal BKWL.
The page buffer 60 senses the voltage of the bit line BL and outputs the voltage to an element external to the memory device, and/or provides the bit line BL with operational voltages received from an external source.
In the conventional non-volatile semiconductor memory device, the voltage level of the block gating signal BKWL is adjusted in accordance with a boosting method. As shown in FIG. 2, throughout a programming process the voltage level of the block gating signal BKWL during a programming operation is greater than the voltage level of the block gating signal BKWL during a preceding programming operation (except for the first programming operation, which has no preceding programming operation). Therefore, the conventional non-volatile semiconductor memory device suffers a drawback in that the voltage level of the block gating signal BKWL is unstable and difficult to control.
Further, in the conventional non-volatile semiconductor memory device, at the starting point of each programming operation 61, 71, and 81, and each verify read operation 62, 72, and 82, the block gating signal BKWL is discharged to a ground voltage VSS. Therefore, the conventional non-volatile semiconductor memory device suffers another drawback in that unnecessary current is consumed and/or a data programming time is increased.